1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof.
2. Description of the Related Art
In current semiconductor integrated circuits, the characteristics of the transistors forming the circuit are improved by increasing carrier mobility through application of stress to the channel region using stressing film material (see, for example, JP-A-2005-57301, and JP-T-2008-539591). A simulation technique to calculate the electron state of the carriers taking into account strains caused by the applied stress to the channel also has been realized (see, for example, JP-A-2008-527745).
As described in these publications, the techniques of the related art propose the method of improving transistor characteristics using stressing film material, and the method of grasping the electron state of the carriers using stress. However, MOSFETs have not been realized that optimize the positional relationship between the applied stress to the channel region and the electron state in the vicinity of the source region. As such, attempts to improve characteristics using the applied stress to the channel region have not been effective.
A technique of related art using a process generally known as a gate first process in which the gate electrode is formed before the source region and drain region is described below with reference to, for example, the schematic cross sectional view, the carrier concentration distribution diagram, the potential distribution diagram, and the stress distribution diagram of FIG. 13.
As illustrated in (1) in FIG. 13, a gate electrode 114 is formed on a semiconductor substrate 111 via a gate insulating film 113.
A first side-wall insulating film 115 is formed on side walls of the gate electrode 114. A source-side extension region 116 is formed in the semiconductor substrate 111 on one side of the gate electrode 114, and a drain-side extension region 117 is formed in the semiconductor substrate 111 on the other side. The source-side extension region 116 and the drain-side extension region 117 are formed so as to intrude into regions underneath the end portions of the gate electrode 114.
A second side-wall insulating film 118 is formed on the both sides of the gate electrode 114 via the first side-wall insulating film 115. A source region 119 is formed via the source-side extension region 116 on one side of the gate electrode 114, and a drain region 120 is formed via the drain-side extension region 117 on the other side of the gate electrode 114. The source region 119 and the drain region 120 are formed in such a manner that the source-side extension region 116 and the drain-side extension region 117 remain underneath the second side-wall insulating film 118.
A first stress-introducing layer 121 (121S, 121D) is formed in regions of the semiconductor substrate 111 where the source region 119 and the drain region 120 are formed. For example, the source region 119 and the drain region 120 are formed in the first stress-introducing layer 121S and the first stress-introducing layer 121D, respectively. The first stress-introducing layer 121 ends substantially below the end portion of the second side-wall insulating film 118.
A silicide layer 122 is formed on the gate electrode 114, the source region 119, and the drain region 120.
A second stress-introducing layer 123 is formed so as to cover the gate electrode 114, the source region 119, and the drain region 120. An interlayer insulating film 124 is formed on the second stress-introducing layer 123.
In a semiconductor device 101 of the foregoing configuration, a channel region 112 is formed in the semiconductor substrate 111 between the source region 119 and the drain region 120.
In the semiconductor device 101 of the foregoing configuration, as represented in (2) in FIG. 13, the peaks of the carrier concentration distributions in the source-side extension region 116 and the drain-side extension region 117 occur inward of the end portions of the gate electrode 114 with respect to the gate length direction, in order to improve short channel characteristics.
Accordingly, as represented in (3) in FIG. 13, the peak of the potential distribution that occurs in the vicinity of the source-side extension region 116 is positioned more inward. Note that (3) in FIG. 13 represents a potential distribution of a conduction band under application of a positive potential to the drain with respect to the source in an nFET.
On the other hand, as represented in (4) in FIG. 13, the peaks in the distribution of the applied stress to the channel region 112 from the first stress-introducing layer 121 and the second stress-introducing layer 123 occur at the end portions of the second side-wall insulating film 118 on the side of the source region 119 and the drain region 120. In this manner, the stress introducing films create a discontinuous stress distribution in the channel region (see, for example, D. Kosemura et al., Characterization of Strain for High Performance MOSFETs, SSDM, pp. 390, 2007). Accordingly, the stress distribution of applied stress to the channel region 112 has a peak outward of the impurity boundary between the channel region 112 and the source-side extension region 116 (toward the source region 119).